This invention relates to a semiconductor memory device and, in particular, to a non-volatile semiconductor memory device including a writing or erasing time interval determining circuit.
Conventionally, in the non-volatile semiconductor memory device, such as an electrically erasable programmable read only memory (EEPROM), a data writing or erasing time interval is determined by a pulse signal having a predetermined pulse width. The pulse width is determined during design processes for development of the non-volatile semiconductor memory device. The pulse width is also determined based on a result of samples test. When the pulse width is determined in the above-mentioned manners, a method of controlling the pulse width is generally employed in order to prevent incomplete writing or erasing operations. In the method, the pulse width is determined to have a spare time so that data writing or erasing operation is completed in a memory cell.
In addition to the method of controlling the writing or erasing operation in which a predetermined writing or erasing time interval is reserved, another method of controlling writing or erasing operation is proposed in Japanese Unexamined Patent Publication No. Sho 60-236195, namely, 236195/1985, as will later be described in detail.
However, even in the aforesaid methods of controlling the writing or erasing operation, it is difficult that incomplete data writing or erasing operation is perfectly prevented.
In the method of controlling the writing or erasing operation in which the predetermined writing or erasing time interval is reserved, the above-mentioned spare time is determined so as not to be too long in view of users' requirements. When a power source voltage is reduced, it takes a long time that the writing or erasing operation is completely finished. As a result, it becomes impossible that the writing or erasing operation is completely finished within the above-mentioned predetermined pulse width. Thus, the data writing or erasing operation sometimes becomes incomplete in the memory cell. For example, let it be presumed that the writing operation needs 2 ms at a power source voltage of 5.0 V. It may be considered that the predetermined pulse width T of 4 ms has an enough spare time. However, it turns out that the writing operation needs 7 ms at a power source voltage of 3.5 V, although the pulse width T becomes not more than 4.75 ms. It is therefore inevitable that incomplete data writing is caused to occur.
Similar problems cannot be avoided even in the method of controlling writing or erasing operation proposed in the above-referenced Japanese Unexamined Patent Publication No. Sho 60-236195.